A microcomputer is provided with a power-on reset circuit or LVD (Low Voltage Detection) circuit for detecting reduction or interruption of a power supply of the microcomputer. In some cases, however, the state of a power supply in a nonvolatile semiconductor memory which is included in the microcomputer cannot be detected by this power-on reset circuit or LVD circuit, due to a variety of factors such as use of different power supplies, difference in sensitivity to noise, arrangement of components, interconnect lines, for example.
In the nonvolatile semiconductor memory, a variety of voltages are required and generated for controlling write and erase operations. If short interruption of an internal power supply occurs due to a certain factor, failure to be able to detect this abnormality may disadvantageously result in a long time to be taken to discharge remaining electric charge from a specific node to which the generated voltage has been supplied.
In order to overcome the above disadvantage, a scheme for discharging remaining electric charge after interruption of a power supply has been proposed.
For example, PTD 1 (Japanese Patent Laying-Open No. 2010-232848) discloses a scheme for discharging, in the following manner, electric charge remaining after interruption of a power supply.
A discharge circuit is configured so that it includes a plurality of NMOS transistors for the sake of discharge, an NMOS transistor for the sake of potential compensation, and a DMOS transistor for reducing the potential of an interconnect line by a coupling capacitor. When a power supply voltage is interrupted, the DMOS transistor and the potential-compensation NMOS transistor reduce the potential of the interconnect line to a negative potential, and a plurality of discharge NMOS transistors operate to reduce and discharge remaining electric charge of the interconnect line.